A variable-pipeline on-chip router optimized to traffic pattern.
Yuto HirataHiroki MatsutaniMichihiro KoibuchiHideharu AmanoPublished in: NoCArc@MICRO (2010)
Keyphrases
- network on chip
- routing algorithm
- flow control
- pattern matching
- network layer
- end to end
- high speed
- multi processor
- programmable logic
- low cost
- network simulator
- network devices
- network traffic
- ip address
- traffic flow
- real time
- packet forwarding
- analog vlsi
- single chip
- pipeline architecture
- content addressable memory
- power dissipation
- traffic management
- ip networks
- pattern discovery
- response time
- moving objects