A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip interconnects.
Eisse MensinkDaniël SchinkelEric A. M. KlumperinkEd van TuijlBram NautaPublished in: ISSCC (2007)
Keyphrases
- cmos technology
- low power
- ultra low power
- high speed
- power dissipation
- clock frequency
- low voltage
- power consumption
- nm technology
- silicon on insulator
- low cost
- mixed signal
- parallel processing
- rms error
- image sensor
- single chip
- average error
- frequency response
- digital signal processing
- cmos image sensor
- chip design
- low power consumption
- data acquisition