Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching.
Chung-Ping ChenNoel MenezesPublished in: DAC (1999)
Keyphrases
- high speed
- noise level
- graph matching
- low cost
- signal to noise ratio
- noise reduction
- power dissipation
- shape matching
- hierarchical structure
- missing data
- matching algorithm
- random noise
- noisy data
- image matching
- feature matching
- noise model
- feature points
- vlsi implementation
- power consumption
- input output
- coarse to fine
- pattern matching
- matching process
- single chip