Blue Gene/L compute chip: Memory and Ethernet subsystem.
Martin OhmachtReinaldo A. BergamaschiSubhrajit BhattacharyaAlan GaraMark GiampapaBalaji GopalsamyRuud A. HaringDirk HoenickeDavid J. KrolakJames A. MarcellaBen J. NathansonValentina SalapuraMichael E. WazlowskiPublished in: IBM J. Res. Dev. (2005)
Keyphrases
- embedded dram
- high speed
- random access memory
- massively parallel
- low cost
- memory subsystem
- high density
- design considerations
- programmable logic
- computational power
- memory usage
- dynamic random access memory
- main memory
- processor core
- analog vlsi
- real time
- digital signal processors
- ibm eservertm
- low voltage
- memory access
- power dissipation
- tcp ip
- circuit design
- random access
- data transfer
- associative memory