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Exploration of Ternary Logic Using T-CMOS for Circuit-Level Design.
JongHyun Ko
Jongbeom Kim
TaeGam Jeong
Jaehoon Jeong
Taigon Song
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2023)
Keyphrases
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circuit design
chip design
delay insensitive
digital circuits
high speed
logic synthesis
neural network
design methodology
engineering design
cmos technology
logic circuits
electronic circuits
design process
analog vlsi
micron cmos
design space
single chip
power consumption