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JongHyun Ko
ORCID
Publication Activity (10 Years)
Years Active: 2021-2024
Publications (10 Years): 6
Top Topics
Delay Insensitive
Design Methodology
Spiking Neural Networks
Flash Memory
Top Venues
IEEE Trans. Circuits Syst. I Regul. Pap.
ISLPED
Adv. Intell. Syst.
ISMVL
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Publications
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JongHyun Ko
,
Dongseok Kwon
,
Joon Hwang
,
Kyu-Ho Lee
,
Seongbin Oh
,
Jeonghyun Kim
,
Jiseong Im
,
Ryun-Han Koo
,
Jae-Joon Kim
,
Jong-Ho Lee
SNNSim: Investigation and Optimization of Large-Scale Analog Spiking Neural Networks Based on Flash Memory Devices.
Adv. Intell. Syst.
6 (4) (2024)
Jaehoon Jeong
,
Yunjeong Shin
,
Hyundong Lee
,
JongHyun Ko
,
Jongbeom Kim
,
Taigon Song
Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node.
IEEE Access
12 (2024)
Jongbeom Kim
,
Hyundong Lee
,
JongHyun Ko
,
Bongjun Kim
,
Taigon Song
L: A Practical Implementation of Tri-Transistor Ternary Logic Based on Inkjet-Printed Anti-Ambipolar Transistors and CMOSs of Thin-Film Structure.
IEEE Trans. Circuits Syst. I Regul. Pap.
70 (12) (2023)
JongHyun Ko
,
Jongbeom Kim
,
TaeGam Jeong
,
Jaehoon Jeong
,
Taigon Song
Exploration of Ternary Logic Using T-CMOS for Circuit-Level Design.
IEEE Trans. Circuits Syst. I Regul. Pap.
70 (9) (2023)
Jaehoon Jeong
,
JongHyun Ko
,
Taigon Song
A Study on Optimizing Pin Accessibility of Standard Cells in the Post-3 nm Node.
ISLPED
(2022)
JongHyun Ko
,
KwanWoo Park
,
Suhyeong Yong
,
TaeGam Jeong
,
Taehak Kim
,
Taigon Song
An Optimal Design Methodology of Ternary Logic in Iso-device Ternary CMOS.
ISMVL
(2021)