A CMOS Dual-Mode Brain-Computer Interface Chipset With 2-mV Precision Time-Based Charge Balancing and Stimulation-Side Artifact Suppression.
Haoran PuOmid Malekzadeh-ArastehAhmad Reza DaneshZoran NenadicAn H. DoPayam HeydariPublished in: IEEE J. Solid State Circuits (2022)
Keyphrases
- brain computer interface
- evoked potentials
- spinal cord injury
- motor imagery
- charge coupled devices
- signal processing
- healthy subjects
- high speed
- eeg signals
- event related
- brain activity
- computer screen
- eeg data
- power consumption
- machine learning
- motion vectors
- medical images
- brain signals
- neural network
- edge detection
- event related potentials
- charge coupled device
- feature space