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A BIST structure for the evaluation of the MOSFET gate dielectric interface state density in post-processed CMOS chips.
Norman Dodel
Stefan Keil
Andreas Wiemhofer
Malte Kortstock
Philipp Scholz
Uwe Kerst
Roland Thewes
Published in:
ESSCIRC (2015)
Keyphrases
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post processed
high speed
low cost
neural network
usability evaluation
high density
low power
post processing
state space
computer systems
tree structure
power consumption
user friendly
user interface
feature selection
real time
nm technology