Generation of VHDL Code from UML/MARTE Sequence Diagrams for Verification and Synthesis.
Emad Samuel Malki EbeidDavide QuagliaFranco FummiPublished in: DSD (2012)
Keyphrases
- sequence diagrams
- uml models
- class diagrams
- petri net
- activity diagrams
- intermediate representation
- model based testing
- regression testing
- unified modelling language
- class diagram
- hardware description language
- hardware implementation
- test cases
- source code
- model checking
- integrated circuit
- dependency graph
- uml class diagrams
- object oriented
- data structure
- video sequences
- artificial intelligence