Sign in

Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.

Steven M. NowickNiraj K. JhaFu-Chiung Cheng
Published in: VLSI Design (1995)
Keyphrases
  • asynchronous circuits
  • fault diagnosis
  • neural network
  • shortest path
  • model checking
  • robust estimation
  • process algebra
  • delay insensitive
  • genetic algorithm
  • low cost
  • computationally efficient