A 6-Bit 1.5-GS/s SAR ADC With Smart Speculative Two-Tap Embedded DFE in 130-nm CMOS for Wireline Receiver Applications.
Azad MahmoudiPooya TorkzadehMassoud DoustiPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2021)
Keyphrases
- analog to digital converter
- decision feedback
- random access memory
- nm technology
- cmos technology
- synthetic aperture radar
- silicon on insulator
- low power
- high speed
- wireless networks
- image sensor
- dynamic random access memory
- sar images
- received signal
- mixed signal
- metal oxide semiconductor
- embedded systems
- low voltage
- image reconstruction
- low cost
- circuit design
- delay insensitive
- analog vlsi
- parallel processing
- end to end
- video sequences