Towards Trainable Synthesis for Optimized Circuit Deployment on FPGA.
Jean-Philippe LegaultPanagiotis PatrosKenneth B. KentPublished in: RSP (2018)
Keyphrases
- high speed
- analog circuits
- gate array
- power reduction
- logic synthesis
- hardware implementation
- hardware description language
- low cost
- verilog hdl
- program synthesis
- texture synthesis
- digital circuits
- computer vision
- field programmable gate array
- low power
- logic circuits
- signal processing
- real time
- parallel architecture
- fault diagnosis
- hardware architectures
- video sequences
- systolic array
- case study