Scalable bus interface for HSDPA co-processor extension.

Toshiki Takeuchi Hiroyuki Igura Takeshi Hashimoto Soichi Tsumura Naoki Nishi

Published in: CICC (2005)

Keyphrases

high speed
user interface
user friendly
genetic algorithm
web scale
single chip
multi core processors
multi processor
lightweight
parallel processing
packet loss
computer architecture
graphical interface
direct manipulation
functional verification