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A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool.

Nazanin MansouriRanga Vemuri
Published in: FMCAD (1998)
Keyphrases
  • automated verification
  • high level synthesis
  • model checking
  • design space exploration
  • automated reasoning
  • design tools
  • formal verification
  • parallel architecture
  • natural language
  • design space