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Power Performance Profiling of 3-D Stencil Computation on an FPGA Accelerator for Efficient Pipeline Optimization.
Koji Okina
Rie Soejima
Kota Fukumoto
Yuichiro Shibata
Kiyoshi Oguri
Published in:
SIGARCH Comput. Archit. News (2015)
Keyphrases
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efficient computation
field programmable gate array
real time
computationally efficient
optimization algorithm
lightweight
data acquisition
optimization method
neural network
wireless sensor networks
simulated annealing
computationally expensive
efficient implementation
constrained optimization
hardware design