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A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor.
Takashi Okuda
Isao Naritake
Tadahiko Sugibayashi
Yuji Nakajima
Tatsunori Murotani
Published in:
IEEE J. Solid State Circuits (2000)
Keyphrases
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memory subsystem
ibm zenterprise
instruction set
dynamic random access memory
input output
instruction set architecture
main memory
processor core
embedded dram
floating point
random access memory
network simulator
database
high speed
higher throughput