Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections.
Kevin T. TangEby G. FriedmanPublished in: Integr. (2000)
Keyphrases
- noise estimation
- logic circuits
- power dissipation
- noise level
- low power
- delay insensitive
- power consumption
- noisy images
- denoising
- low cost
- chip design
- high speed
- random access memory
- wyner ziv video coding
- high density
- cmos technology
- additive noise
- asynchronous circuits
- noise reduction
- low voltage
- edge detection
- similarity measure