A Sub-Sampling Phase Detector for Low-Power PAM4 Clock Recovery Circuit.
Alok KumarShalabh GuptaPublished in: MWSCAS (2023)
Keyphrases
- low power
- high speed
- power consumption
- logic circuits
- cmos technology
- power reduction
- power dissipation
- single chip
- wireless transmission
- high power
- low cost
- vlsi circuits
- gate array
- delay insensitive
- mixed signal
- digital signal processing
- single phase
- vlsi architecture
- real time
- power saving
- duty cycle
- low power consumption
- image sensor
- energy dissipation
- nm technology
- video sequences