A Support Vector Regression (SVR)-Based Latency Model for Network-on-Chip (NoC) Architectures.
Zhiliang QianDa-Cheng JuanPaul BogdanChi-Ying TsuiDiana MarculescuRadu MarculescuPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2016)