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A 1.5 V 2 GS/s 82.1 dB-SFDR Track and Hold Circuit Based on the Time-Divided Post-Distortion Cancelation Technique.
Junyoung Jang
Youngcheol Chae
Tae Wook Kim
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2022)
Keyphrases
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high speed
database
noise ratio
electronic circuits
analog vlsi
evolutionary algorithm
single phase
circuit design
hearing aids
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duty cycle
digital circuits
geometric distortions
information loss
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moving objects