A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller.
Gianfranco GerosaMike AlexanderJose AlvarezCody CroxtonMichael D'AddeoA. Richard KennedyCarmine NicolettaJames P. NissenRoss PhilipPaul ReedHector SanchezScott A. TaylorBrad BurgessPublished in: IEEE J. Solid State Circuits (1997)
Keyphrases
- memory subsystem
- high speed
- processor core
- operating system
- silicon on insulator
- cmos technology
- ibm zenterprise
- functional verification
- control system
- real time
- circuit design
- physical design
- clock frequency
- low power
- instruction set
- control method
- embedded dram
- control scheme
- closed loop
- cache misses
- control algorithm
- input output
- dynamic random access memory
- memory access
- multithreading
- control strategy
- data access
- response time
- neural network
- prefetching
- gigabit ethernet