CMOS Design of Two Winner-Take-All Circuits Using Pulse Duty Cycle Synaptic Weighting.

Gyu Moon Mona E. Zaghloul R. W. Newcomb

Published in: ISCAS (1994)

Keyphrases

circuit design
high speed
design process
low cost
power consumption
digital circuits
power dissipation
cmos technology
delay insensitive
mobile devices
data management
chip design
duty cycle