A 1.5 V 23 MHz low power FGMOS filter.

Esther Rodríguez-Villegas Adoración Rueda Alberto Yúfera

Published in: ICECS (2001)

Keyphrases

low power
high speed
cmos technology
low cost
power consumption
high power
deblocking filter
single chip
nm technology
low power consumption
vlsi architecture
vlsi circuits
wireless transmission
logic circuits
gate array
power dissipation
digital signal processing
power reduction
edge detection