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A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40 nm CMOS process.
Chua-Chin Wang
Chiang-Hsiang Liao
Sih-Yu Chen
Published in:
ISCAS (2014)
Keyphrases
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sensor networks
neural network
leakage current
low power
genetic algorithm
sensor data
power consumption