An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires.

Ya-Chi Huang Meng-Hsueh Chiang Shui-Jinn Wang Sumeet Kumar Gupta

Published in: ICICDT (2018)

Keyphrases

low voltage
cmos technology
leakage current
power consumption
design considerations
cost effective
random access memory
multimedia
low cost
signal to noise ratio