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Crosstalk delay analysis of a 0.13-μm node test chip and precise gate-level simulation technology.

Yasuhiko SasakiMitsumasa SatoMasaru KuramotoFujio KikuchiTsutomu KawashimaHiroo MasudaKazuo Yano
Published in: IEEE J. Solid State Circuits (2003)
Keyphrases
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