A fault tolerant test hardware for L1 cache module in tile CMPs architecture.
Saha MousumiNavneet Kumar GautamBiplab K. SikdarPublished in: VDAT (2015)
Keyphrases
- fault tolerant
- fault tolerance
- memory hierarchy
- host computer
- distributed systems
- multithreading
- hardware architecture
- memory access
- load balancing
- memory management
- evolvable hardware
- low cost
- main memory
- hardware implementation
- hardware and software
- error detection
- memory subsystem
- shared memory
- computer systems
- state machine
- high availability
- management system
- interconnection networks
- multimedia
- prefetching
- fault isolation
- embedded processors
- peer to peer