A 1.2 TB/s on-chip ring interconnect for 45nm 8-core enterprise Xeon® processor.
Cheolmin ParkRoy BadeauLarry BiroJonathan ChangTejpal SinghJim VashBo WangTom WangPublished in: ISSCC (2010)
Keyphrases
- high speed
- single chip
- clock frequency
- ibm power processor
- cmos technology
- processor core
- low power
- power dissipation
- chip design
- silicon on insulator
- functional verification
- dynamic random access memory
- information management
- low cost
- nm technology
- power consumption
- random access memory
- vlsi implementation
- level parallelism
- analog vlsi
- ibm zenterprise
- real time
- ibm eservertm
- embedded dram
- power reduction
- information systems