Accurate Calculation of Unreliability of CMOS Logic Cells and Circuits.
Azam BegPublished in: J. Circuits Syst. Comput. (2020)
Keyphrases
- delay insensitive
- chip design
- floating gate
- random access memory
- asynchronous circuits
- high speed
- analog vlsi
- logic synthesis
- circuit design
- logic circuits
- digital circuits
- vlsi circuits
- low power
- low voltage
- high accuracy
- high quality
- classical logic
- visual cortex
- power consumption
- computationally efficient
- low cost
- cancer cells
- logic programming
- built in self test