A 10-BIT 100MS/s pipelined ADC IN 0.18μm CMOS technology.
Hwei-Yu LeeShen-Iuan LiuPublished in: SoCC (2007)
Keyphrases
- cmos technology
- spl times
- analog to digital converter
- low power
- mixed signal
- image sensor
- low voltage
- random access memory
- power consumption
- flip flops
- single chip
- embedded dram
- parallel processing
- cmos image sensor
- power dissipation
- high speed
- multi channel
- low cost
- hardware and software
- data flow
- video camera
- pattern recognition
- digital signal processing
- dynamic range
- digital images