Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs.
Naifeng JingJianfei WangFengfeng FanWenkang YuLi JiangChao LiXiaoyao LiangPublished in: MICRO (2016)
Keyphrases
- memory access
- memory subsystem
- embedded dram
- multithreading
- memory hierarchy
- random access memory
- dynamic random access memory
- data access
- memory management
- main memory
- level parallelism
- memory bandwidth
- distributed memory
- instruction set
- processing units
- cache misses
- embedded processors
- processor core
- single chip
- design considerations
- ibm zenterprise
- parallel computing
- signal processor
- cmos technology
- computing power
- access patterns
- database
- speculative execution
- read write
- external memory
- vlsi implementation
- computer architecture
- management system