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A 10nm SRAM Design using Gate-Modulated Self-Collapse Write Assist Enabling 175mV VMIN Reduction with Negligible Power Overhead.

Zheng GuoJami WiedemerYusung KimPrithvee Sundararajan RamamoorthyPrateeksha Bindiganavile SathyaprasadSmita ShridharanDaeyeon KimEric Karl
Published in: VLSI Circuits (2020)
Keyphrases
  • cmos technology
  • power consumption
  • power reduction
  • nm technology
  • design process
  • low power
  • engineering design
  • data sets
  • expert systems
  • user interface