4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor.
Penny LiJinuk Luke ShinGeorgios K. KonstadinidisFrancis SchumacherVenkatram KrishnaswamyHoyeol ChoSudesna DashRobert P. MasleidChaoyang ZhengYuanjung David LinPaul LoewensteinHeechoul ParkVijay SrinivasanDawei HuangChangku HwangWenjay HsuCurtis McAllisterPublished in: ISSCC (2015)
Keyphrases
- processor core
- dynamic random access memory
- memory hierarchy
- embedded processors
- cache misses
- shared memory multiprocessors
- prefetching
- memory subsystem
- shared memory multiprocessor
- multithreading
- high speed
- operating system
- computer architecture
- memory management
- database workloads
- memory access
- instruction set
- inter frame
- query processing
- read write
- database systems
- single chip
- shared memory