Login / Signup
A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS.
Bob Verbruggen
Jan Craninckx
Maarten Kuijk
Piet Wambacq
Geert Van der Plas
Published in:
ISSCC (2010)
Keyphrases
</>
power consumption
analog to digital converter
power supply
hd video
circuit design
metal oxide semiconductor
low power
high speed
dynamic environments
low cost
power plant
single chip
high definition
nm technology