Low power asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL).
Jin-Kyung LeeKyung Ki KimPublished in: MWSCAS (2017)
Keyphrases
- low power
- circuit design
- delay insensitive
- low cost
- power consumption
- cmos technology
- logic circuits
- high speed
- digital circuits
- asynchronous circuits
- single chip
- mixed signal
- vlsi circuits
- nm technology
- wireless transmission
- low power consumption
- high power
- power dissipation
- design automation
- energy dissipation
- ultra low power
- signal processor
- digital camera
- low voltage
- vlsi architecture
- data flow
- image sensor