Test Scheduling for Network-on-Chip with BIST and Precedence Constraints.
Chunsheng LiuHamid SharifÉrika F. CotaDhiraj K. PradhanPublished in: ITC (2004)
Keyphrases
- precedence constraints
- scheduling problem
- branch and bound algorithm
- precedence relations
- parallel machines
- release dates
- parallel processors
- approximation algorithms
- network on chip
- single machine scheduling problem
- maximum lateness
- global constraints
- partial order
- single machine
- partially ordered
- built in self test
- unit length
- flowshop
- branch and bound
- parallel algorithm