A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure.

Simon D. Haynes Peter Y. K. Cheung

Published in: FCCM (1998)

Keyphrases

image processing tasks
hardware implementation
video sequences
systolic array
feature detection
low cost
image processing
field programmable gate array
digital signal
high frequency
multiscale
signal processing