A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO.
Wanghua WuChih-Wei YaoChengkai GuoPei-Yuan ChiangLei ChenPak-Kim LauZhanjun BaiSang Won SonThomas Byunghak ChoPublished in: IEEE J. Solid State Circuits (2021)