FPGA-Based Clock Phase Alignment Circuit for Frame Jitter Reduction.

Dario Russo Stefano Ricci

Published in: ApplePies (2019)

Keyphrases

high speed
duty cycle
power consumption
frame rate
power reduction
single phase
reduction method
neural network
circuit design
end to end delay
hardware implementation
video frames
image frames
field programmable gate array
hardware architecture
digital circuits
preprocessing phase
analog vlsi
general purpose