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Design of a Novel Self-Test-on-Chip Interface ASIC for Capacitive Accelerometers.
Xiangyu Li
Pengjun Wang
Gang Li
Yuejun Zhang
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2023)
Keyphrases
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physical design
circuit design
single chip
design methodology
user interface
design process
functional verification
embedded systems
low power
experimental design
neural network
chip design
design patterns
hardware implementation
human computer interface
high speed
low cost
hardware architecture
built in self test