A 68.36 dB 12 bit 100MS/s SAR ADC with a low-noise comparator in 14-nm CMOS FinFet.
Yan ZhengJingchao LanFan YeJunyan RenPublished in: ASICON (2021)
Keyphrases
- analog to digital converter
- high noise
- low signal to noise ratio
- nm technology
- low cost
- random access memory
- signal to noise ratio
- low power
- mixed signal
- power consumption
- random noise
- signal subspace
- noise level
- high speed
- synthetic aperture radar
- noisy data
- missing data
- single chip
- sar images
- cmos technology
- noise reduction
- silicon on insulator
- received signal
- multiplicative noise
- power supply
- speckle noise