An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor.
Yohei HasegawaShohei AbeHiroki MatsutaniHideharu AmanoKenichiro AnjoToru AwashimaPublished in: FPT (2005)
Keyphrases
- smart card
- high speed
- network security
- parallel processing
- security protocols
- multiprocessor systems
- hash functions
- parallel implementation
- single processor
- computer architecture
- processor core
- random number generator
- parallel architectures
- parallel processors
- authentication protocol
- key management
- intrusion detection system
- input output
- lightweight