Login / Signup
Techniques for minimizing power dissipation in scan and combinational circuits during test application.
Vinay Dabholkar
Sreejit Chakravarty
Irith Pomeranz
Sudhakar M. Reddy
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1998)
Keyphrases
</>
power dissipation
logic circuits
power reduction
power consumption
low power
cmos technology
analog circuits
chip design
high speed
input output
digital camera
massively parallel
asynchronous circuits
vlsi circuits