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An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator without Accuracy Loss in 28nm CMOS.
Ziyu Li
Weiwei Shan
Chengjun Wu
Haitao Ge
Jun Yang
Published in:
A-SSCC (2021)
Keyphrases
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error detection
neural network
error correction
highly accurate
data cleansing
error recovery
artificial neural networks
high speed
computational complexity
positive and negative
parallel implementation
error control
training data
low cost
error propagation
fault isolation