2-D Array processor having a controlled pipelined architecture for elliptical sparse matrices.
Costas E. GoutisJ. S. ShebleeG. RussellPublished in: ICASSP (1985)
Keyphrases
- array processor
- sparse matrices
- pipelined architecture
- semantic network
- scan line
- floating point
- linear algebra
- hardware implementation
- condition number
- field programmable gate array
- rows and columns
- real time
- parallel computing
- biologically motivated
- computing systems
- signal processing
- linear relaxation
- multiresolution
- image processing
- knowledge base