Gate delay modeling for pre- and post-silicon timing related tasks for ultra-low power CMOS circuits.
Prasanjeet DasSandeep K. GuptaPublished in: ICCD (2013)
Keyphrases
- cmos technology
- low power
- power dissipation
- ultra low power
- high speed
- power consumption
- low cost
- low voltage
- delay insensitive
- nm technology
- circuit design
- gate dielectrics
- logic circuits
- chip design
- image sensor
- field effect transistors
- mixed signal
- analog vlsi
- vlsi circuits
- parallel processing
- asynchronous circuits
- flip flops
- digital signal processing