Backdrive Stress-Testing of CMOS Gate Array Circuits.
Frank H. HielscherJohn C. PaganoPublished in: ITC (1985)
Keyphrases
- gate array
- low power
- logic circuits
- high speed
- delay insensitive
- power consumption
- cmos technology
- analog vlsi
- circuit design
- vlsi circuits
- low cost
- power dissipation
- mixed signal
- chip design
- focal plane
- low voltage
- logic synthesis
- test cases
- single chip
- floating gate
- digital signal processing
- random access memory
- digital circuits
- stress distribution
- wide dynamic range