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A 15 µm-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory.
Dong-Hwan Jin
Ji-Wook Kwon
Hyeon-June Kim
Sun-Il Hwang
Min-Chul Shin
Junho Cheon
Seung-Tak Ryu
Published in:
IEEE J. Solid State Circuits (2015)
Keyphrases
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high speed
single phase
memory requirements
data sets
real time
associative memory
memory size
learning phase
duty cycle
analog circuits
circuit design
limited memory
memory usage
training phase
worst case
np hard
lower bound