Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product.
I-Cheng LinChih-Yao HuangChuan-Jane ChaoMing-Dou KerPublished in: Microelectron. Reliab. (2003)
Keyphrases
- high voltage
- analog vlsi
- circuit design
- high speed
- phase locked loop
- cmos technology
- integrated circuit
- metal oxide semiconductor
- power dissipation
- operating conditions
- chip design
- anomaly detection
- low power
- power consumption
- nm technology
- partial discharge
- low cost
- focal plane
- low voltage
- normal operation
- digital circuits
- vlsi circuits
- evolvable hardware
- cmos image sensor
- steady state
- silicon on insulator
- delay insensitive
- mixed signal
- control system