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A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology.

Anant SinghMichael CiraulaDon WeissJohn WuuPhilippe BauserPaul de ChampsHamid DaghighianDavid FischPhilippe GraberMichel Bron
Published in: ISSCC (2009)
Keyphrases
  • silicon on insulator
  • dynamic random access memory
  • case study
  • memory subsystem
  • data transfer
  • storage devices
  • embedded systems
  • hard disk
  • data structure
  • low cost
  • cmos technology